1. Field of the Invention
This invention relates to a memory buffer and particularly to a memory buffer for utilization in a digital signal processor.
2. Prior Art
In the prior art there exists several schemes and devices for buffering a relatively slow external memory to a relatively fast processor unit. Such schemes and devices include the simplest register which consists of some predetermined small number of bits to a large cache memory. Furthermore, such registers or cache memories have been implemented utilizing hardware and software.
While such memory buffering schemes or devices have the capability of providing the instructions of a program to a processor at a relatively high rate when compared to the speed of the external memory, such devices all suffer from a major disadvantage in that none of them are capable of satisfying all of the various fetching requirements for the processing unit. In particular, the processing unit may require a fetch from a repetitive program loop and such a fetch is handled efficiently by a cache memory, but inefficiently by a register. Also a processor unit may request non-repetitive instructions from a particular sequence and such a fetch is efficiently handled by a register, but not by a cache memory. In addition, the prior art memory buffering schemes or devices only buffer instructions as they are executed and therefore the instruction must be executed before its instruction type can be determined. As a result, such prior art memory buffering schemes ignore program flow. Finally, the processor unit may request an instruction which is a conditional jump or branch and such an instruction is not handled efficiently by either a cache memory or register.